Semiconductor transistor having a stressed channel

ABSTRACT

A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases I DSAT  and I DLIN  of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

BACKGROUND OF THE INVENTION

[0001] 1). Field of the Invention

[0002] This invention relates to the field of semiconductormanufacturing, and more specifically to a semiconductor transistor andits manufacture.

[0003] 2). Discussion of Related Art

[0004] Integrated circuits are often manufactured in and on silicon andother semiconductor wafers. Such integrated circuits include literallymillions of metal oxide semiconductor (MOS) field effect transistors,having gate lengths on the order of 0.05 microns. Such MOS transistorsmay include p-channel MOS (PMOS) transistors, and n-channel MOS (NMOS)transistors, depending on their dopant conductivity types.

[0005] Wafers are obtained by drawing an ingot of silicon out of aliquid silicon bath. The ingot is made of monocrystalline(single-crystal) silicon, and is subsequently sawed into individualwafers. A layer of silicon is then deposited over each wafer. Becausethe wafer is made of monocrystalline silicon, the deposition conditionscan be controlled so that the layer of silicon deposits “epitaxially”over the wafer. “Epitaxy” refers to the manner in which the siliconlayer deposits on the wafer—the layer of silicon has a lattice which hasa structure which follows a structure of a lattice of themonocrystalline silicon of the wafer. The layer of silicon is alsosubstantially the same material as the monocrystalline silicon of thewafer, so that the lattice of the silicon layer also has substantiallythe same spacing as the spacing of the lattice of the monocrystallinesilicon of the wafer.

[0006] A gate dielectric layer, a gate electrode, and spacers aresubsequently formed on the layer of silicon. Ions are also implantedinto the layer of silicon, which form source and drain regions onopposing sides of the gate electrode. A voltage can be applied over thesource and drain regions. Current flows from the source region to thedrain region through a channel below the gate dielectric layer when avoltage is applied to the gate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention is described by way of example, with reference tothe accompanying drawings, wherein:

[0008]FIG. 1 is a cross-sectional side view of a partially manufacturedPMOS transistor, including a gate electrode and lightly doped regions onopposing sides of the gate electrode;

[0009]FIG. 2 is a view similar to FIG. 1, after the formation of spacerson opposing sides of the gate electrode;

[0010]FIG. 3 is a view similar to FIG. 2, after the formation of deepersource and drain regions;

[0011]FIG. 4 is a view similar to FIG. 3, after diffusion of the dopedregions in a thermal step;

[0012]FIG. 5 is a view similar to FIG. 4, after a selective etch to formrecesses in the source and drain regions;

[0013]FIG. 6 is a view similar to FIG. 5; after depositing source anddrain films epitaxially in the recesses; and

[0014]FIG. 7 is an enlarged view of a portion of FIG. 6, illustratingstresses that are created by the films.

DETAILED DESCRIPTION OF THE INVENTION

[0015] A process is described for manufacturing an improved PMOSsemiconductor transistor. Recesses are etched into a layer of epitaxialsilicon. Source and drain films are deposited in the recesses. Thesource and drain films are made of an alloy of silicon, germanium, andboron incorporated during deposition. By incorporating boron duringdeposition, a higher active dopant concentration can be obtained thanwith implantation techniques. The alloy is epitaxially deposited on thelayer of silicon. The alloy thus has a lattice having the same structureas the structure of the lattice of the layer of silicon. However, due tothe inclusion of the germanium, the lattice of the alloy has a largerspacing than the spacing of the lattice of the layer of silicon. Thelarger spacing creates a stress in a channel of the transistor betweenthe source and drain films. The stress, together with reducedresistivity due to the higher active dopant concentration, increasesI_(DSAT) and I_(DLIN) of the transistor. An NMOS transistor can bemanufactured in a similar manner by including carbon instead ofgermanium, thereby creating a tensile stress. The present invention willbe described with respect to the formation of a PMOS transistor. Oneskilled in the art will appreciate that an NMOS transistor may bemanufactured in a similar manner, except that doping conductivity typesand lattice spacing will be reversed.

[0016]FIG. 1 of the accompanying drawings illustrates an epitaxialsilicon layer 10 which is epitaxially formed on a monocrystalline wafersubstrate. Because the silicon layer 10 is epitaxially formed, itfollows the monocrystalline crystal structure of the wafer substrate.The silicon of the layer 10 is thus also monocrystalline. The siliconlayer 10 includes an n-type dopant, which can be formed by implantingphosphorous and arsenic ions to produce an n-well, having an n-typedopant concentration of approximately 5.0 times 10¹⁸/cm³. (An N+ film isthus created.)

[0017] A plurality of field isolation regions 12 are formed in the layer10. The field isolation regions 12 isolate wells of differentconductivity types, and isolate adjacent transistors. The fieldisolation regions 12 may, for example, be shallow trench isolation (STI)regions formed by etching a trench into the layer 10, and then fillingthe trench with deposited oxide.

[0018] A gate dielectric layer 14 is formed on a top surface 16 of thelayer 10. The gate dielectric layer 14 may be a nitrided oxide layerformed to a thickness of between 5 and 30 Å, preferably approximately 8Å.

[0019] A gate electrode 18 is formed on the gate dielectric layer 14.The gate electrode 18 is preferably between 1,000 and 3,500 Å thick. Thegate electrode 18 may be formed by blanket deposition of polysilicon,and patterning the polysilicon into the gate electrode 18 utilizingknown photolithographic techniques. In the exemplary embodiment, thegate electrode 18 has a width 20 of approximately 89 nm.

[0020] P-dopant ions are subsequently implanted from the top into anexposed upper surface of the layer 10, and into an exposed upper surfaceof the gate electrode 18. The dopant ions may, for example, be boronions. The ions form conductive p-doped regions 22A and 22B. The regions22A and 22B are located on opposing sides of the gate electrode 18, andare spaced from one another by the width 20. A conductive p-doped region24 is also formed in an upper portion of the gate electrode 18.

[0021]FIG. 2 illustrates that spacers 26A and 26B are formed on opposingsides of the gate electrode 18. The spacers 26A and 26B cover sides ofthe gate electrode 18, and also cover portions of the surface 16adjacent and on opposing sides of the gate electrode 18. In the presentexample, the spacers 26A and 26B are L-shaped spacers, the formation ofwhich is known in the art.

[0022] As shown in FIG. 3, upper surfaces of the gate electrode 18 andthe surface 16 are then again implanted with p-dopant ions, typicallyboron ions as in the implantation step of FIG. 1. The implantationenergy is increased, compared to the implantation step of FIG. 1, sothat the boron ions implant deeper into the layer 10. The spacers 26Aand 26B form a mask which prevents implantation of the ions into thelayer 10 below the spacers 26A and 26B. P-doped conductive regions 28Aand 28B are formed by the ions in the layer 10 to a depth deeper thanthe regions 22A and 22B. However, a shallow channel 30 is definedbetween inner edges of the doped regions 22A and 22B resulting from theimplantation step of FIG. 1. The doped region 24 in the gate electrode18 is also deeper after the second implantation step.

[0023] A heat treatment or “annealing” step is subsequently carried out,wherein the structure of FIG. 3 is heated. Heating causes diffusion ofthe regions 22A, 22B, 28A, and 28B into the layer 10. As shown in FIG.4, inner tips 34A and 34B are then located below the gate electrode 18.Lower edges of the regions 28A and 28B move downward into the layer 10.The regions 22A and 22B are epitaxial silicon with a p-dopantconcentration of approximately 1×10¹⁹/cm³. (The regions 22A and 22B arethus doped P−.) No other materials are present in the regions 22A and22B, except silicon, arsenic, phosphorous, and boron. The doped region24 in the gate electrode 18 also diffuses down to the gate dielectriclayer 14.

[0024]FIG. 5 shows the structure of FIG. 4 after a selective etch step.An anisotropic etchant is used which selectively removes silicon overthe other exposed materials of the structure of FIG. 4. Recesses 36A and36B are thereby etched into the regions 28A and 28B. Inner edges of therecesses 36A and 36B are aligned with outer edges of the spacers 26A and26B. Outer edges of the recesses 36A and 36B are at the field isolationregions 12. It should be noted that surfaces 38 of the recesses 36A and36B are monocrystalline epitaxial silicon. Epitaxial silicon has alattice with a known structure and spacing. An upper portion of the gateelectrode 18 is also etched out.

[0025] As shown in FIG. 6, source and drain films 40A and 40B aresubsequently formed in the recesses 36A and 36B. The films 40A and 40Bare epitaxially formed on the surfaces 38. The films 40A and 40B includesilicon, germanium, and boron. The films can be formed in a 200 mmchemical vapor deposition chamber with the following processingconditions: dichlorosilane of 20 sccm, diborane of 70 sccm at 1%concentration, and germane of 50 sccm, at a temperature of 740° C.

[0026] The silicon and the germanium form an alloy having a latticewhich has the same structure as the structure of the lattice of theepitaxial silicon of the surfaces 38. The lattice of the alloy ofsilicon and germanium, however, has a larger spacing than the spacing ofthe lattice of the epitaxial silicon of the surfaces 38, at least in arelaxed state. Because the lattice of the alloy has the same structureas the surfaces 38, the films 40A and 40B form epitaxially on thesurfaces 38. However, because of the larger spacing of the lattice ofthe alloy, the films 40A and 40B create a compressive stress in thechannel 30. The germanium is present in the combination of the siliconand the germanium in about 15 atomic percent. It has been found thatepitaxy can be maintained with a germanium concentration of up to 20atomic percent of the combination of the silicon and germanium byvolume. Epitaxy thus tends to break down at an atomic percentage ofgermanium of above 20 percent. A further advantage of depositing thefilms 40A and 40B is that a relatively large boron concentration can beincluded. The boron concentration is preferably approximately3×10²⁰/cm³. (The films 40A and 40B are thus doped P+.) The relativelylarge concentration of boron creates a relatively low resistance ofapproximately 0.9 mOhm-cm. A conductive p-doped film 42 also deposits onthe etched-back gate electrode 18. Suitable results can be obtained withdopant concentrations of 0.5×10²⁰/cm³ and above. The resistivity ispreferably less than 1.1 mOhm-cm.

[0027]FIG. 7 illustrates the direction of compressive stresses createdby the films 40A and 40B. The directions of the compressive stresses arealong the lines 50. A more dense spacing between the lines 50 indicatesa larger stress, and a larger spacing between the lines 50 indicates asmaller stress. It can be seen that the largest stress is created at ornear the channel 30. The films 40A and 40B extend to a depth 52 into thelayer 10, and are spaced from one another by a width 54. A smaller ratiobetween the depth 52 and the width 54 will result in a smaller stress inthe channel 30, and a larger ratio between the depth 52 and the width 54will result in a larger stress in the channel 30. A ratio between thedepth 52 and the width 54 is preferably at least 0.12, more preferably0.15, more preferably 0.2, and more preferably 0.35. In the presentexample, the depth 52 is 92 nm, and the width 54 is 215 nm.

[0028] The compressive stress reduces the effective mass in the channel,which in turn increases hole mobility. It has been found that acompressive stress in the channel 30 increases the I_(DSAT) of the PMOStransistor 60 by approximately 20 percent. The I_(DLIN) is increased byapproximately 40 percent.

[0029] In the present example, the layer 10 is epitaxial silicon, andthe films 40A and 40B are silicon with a germanium additive. It may bepossible to create similar structures utilizing additives other thangermanium. The present example has also been described with reference toa PMOS transistor. An NMOS transistor may be manufactured in a similarmanner. In an NMOS transistor, doping conductivity types would bereversed. Furthermore, a tensile stress will be created in the channel.A tensile stress can be created utilizing source and drain films ofsilicon which includes carbon. The silicon and carbon form an alloywhich has a lattice with the same structure as the structure of thelattice of the epitaxial silicon, but with a smaller spacing. The sourceand drain films will tend to contract, and create a tensile stress inthe channel.

[0030] While certain exemplary embodiments have been described and shownin the accompanying drawings, it is to be understood that suchembodiments are merely illustrative and not restrictive of the currentinvention, and that this invention is not restricted to the specificconstructions and arrangements shown and described since modificationsmay occur to those ordinarily skilled in the art.

What is claimed:
 1. A semiconductor transistor comprising: a layerhaving source and drain recesses formed therein with a channel betweenthe source and drain recesses, and being made of a semiconductormaterial having a first lattice with a first structure and a firstspacing; a source and a drain formed in the source and drain recessesrespectively, at least one of the source and the drain being made of afilm material which: (a) includes a dopant selected from one of ap-dopant and an n-dopant; and (b) is formed epitaxially on thesemiconductor material so as to have a second lattice having a secondstructure which is the same as the first structure, the second latticehaving a second spacing which differs from the first spacing; a gatedielectric layer on the channel; and a conductive gate electrode on thegate dielectric layer.
 2. The semiconductor transistor of claim 1wherein: (a) if the dopant is a p-dopant, the second spacing is largerthan the first spacing; and (b) if the dopant is an n-dopant, the secondspacing is smaller than the first spacing.
 3. The semiconductortransistor of claim 1 wherein the difference between the first spacingand the second spacing creates a stress in the channel.
 4. Thesemiconductor transistor of claim 1 wherein the second material includesthe semiconductor material and an additive, the difference between thefirst spacing and the second spacing being due to the additive.
 5. Thesemiconductor transistor of claim 4 wherein the semiconductor materialis silicon and the additive is selected from one of germanium andcarbon.
 6. The semiconductor transistor of claim 5 wherein the additiveis germanium.
 7. The semiconductor transistor of claim 6 wherein thegermanium comprises between 1 and 20 atomic percent of the silicon andthe germanium of the film material.
 8. The semiconductor transistor ofclaim 7 wherein the germanium comprises approximately 15 atomic percentof the silicon and the germanium of the film material.
 9. Thesemiconductor transistor of claim 4, further comprising: tip regionsformed between the source and the drain with the channel between the tipregions, the tip regions being formed by implanting of dopants andexcluding the additive.
 10. The semiconductor transistor of claim 9wherein: (a) if the dopant of the film material is a p-dopant, thedopants of the tip regions are p-dopants; and (b) if the dopant of thefilm material is an n-dopant, the dopants of the tip regions aren-dopants.
 11. The semiconductor transistor of claim 1 wherein thedopant comprises at least 0.5×10²⁰/cm³ of the film material.
 12. Thesemiconductor transistor of claim 11 wherein the film material has aresistivity of less than 1.1 mOhm-cm.
 13. The semiconductor transistorof claim 1 wherein the source and drain have a depth into the layer andare spaced by a width from one another, a ratio of the depth to thewidth being at least 0.12.
 14. The semiconductor transistor of claim 13wherein the ratio is at least 0.15.
 15. The semiconductor transistor ofclaim 14 wherein the ratio is at least 0.2.
 16. The semiconductortransistor of claim 15 wherein the ratio is at least 0.35.
 17. Thesemiconductor transistor of claim 16 wherein the ratio is approximately92/215.
 18. A semiconductor transistor comprising: a layer having sourceand drain recesses formed therein with a channel between the source anddrain recesses and being made of a semiconductor material having a firstlattice with a first structure and a first spacing; a source and a drainformed in the source and drain recesses respectively, at least one ofthe source and the drain being made of film material which: (a) includesa dopant selected from one of a p-dopant and an n-dopant; and (b) isformed epitaxially on the semiconductor material so as to have a secondlattice having a second structure which is the same as the firststructure; and (i) if the dopant is a p-dopant, the second lattice has asecond spacing which is larger than the first spacing, so that acompressive stress is created between the source and the drain in thechannels; and (ii) if the dopant is an n-dopant, the second lattice hasa second spacing which is smaller than the first spacing, so that atensile stress is created between the source and the drain in thechannel; a gate dielectric layer on the channel; and a conductive gateelectrode on the gate dielectric layer.
 19. The semiconductor transistorof claim 18 wherein the film material includes the semiconductormaterial and an additive, wherein: (a) if the dopant is a p-dopant, thesecond spacing is larger than the first spacing due to the additive; and(b) if the dopant is an n-dopant, the second spacing is smaller than thefirst spacing due to the additive.
 20. The semiconductor transistor ofclaim 19 wherein: (a) if the dopant is a p-dopant, the additive isgermanium; and (b) if the dopant is an n-dopant, the additive is carbon.21. A semiconductor transistor comprising: a layer having source anddrain recesses formed therein with a channel between the source anddrain recesses, the layer being made of a semiconductor material; asource and a drain formed in the source and drain recesses respectively,the source and the drain being made of a film material which includes adopant selected from one of a p-dopant and an n-dopant, the source andthe drain having a depth into the layer and being spaced by a width fromone another, a ratio between the depth and the width being at least0.12; a gate dielectric layer on the channel; and a conductive gateelectrode on the gate dielectric layer.
 22. The semiconductor transistorof claim 21 wherein the ratio is at least 0.35.
 23. The semiconductortransistor of claim 21 wherein the depth is at least 80 nm.
 24. Thesemiconductor transistor of claim 21 wherein the width is less than 220nm.
 25. A method of forming a transistor comprising: forming a gatedielectric layer on a layer of semiconductor material; forming a gateelectrode on the gate dielectric layer; implanting dopants into thelayer of semiconductor material to form doped tip regions in the layerwith a channel between the tip regions; etching the layer to form sourceand drain recesses in the layer with the tip regions between therecesses; and filling the source and drain recesses with a source and adrain respectively.
 26. The method of claim 25 wherein at least one ofthe source and the drain is made of a film material which: (a) includesa dopant selected from one of a p-dopant and an n-dopant; and (b) isformed epitaxially on the semiconductor materials.
 27. The method ofclaim 25 wherein the source and drain have a depth into the layer andare spaced by a width from one another, a ratio of the depth to thewidth being at least 0.12.